This description relates to admission control for memory access requests.
Modern processors support ‘speculative’ memory access requests. For example, a speculative memory access request may include prefetch requests that are sent to preload an instruction cache or data cache based on a predicted access pattern. Prefetch requests can include a ‘software prefetch’ where an explicit prefetch instruction inserted into a processor's pipeline includes a particular address to be prefetched, or a ‘hardware prefetch’ performed by hardware within the processor without an explicit prefetch instruction being inserted into its pipeline. Speculative memory access requests may also include load or store instructions issued within a pipeline to earlier than the pipeline would have normally issued the instruction without speculation, to improve performance. For example, branch prediction can be used to speculatively issue a load or store instruction before a branch condition of a branch instruction has been determined. However, these speculative memory access requests may not be correct. For example, a speculative load instruction could be unused, or even terminated before it has completed, if the pipeline is flushed after a misprediction. Prefetch requests may bring data/instructions into a data/instruction cache without that data/instruction being immediately used, making a particular prefetch request useless. Some processors may be configured to perform prefetch throttling, where congestion and prefetch accuracy are taken into account as feedback for throttling a source of prefetch requests. However, some techniques for measuring congestion may have certain limitations or may even exacerbate the congestion, as described in more detail below.